ACADSTAFF UGM
| Title | : | Technical Implementation of Dual Mode Fault Tolerance |
| Author | : |
Haryono (1) Prof. Dr. Ir. Jazi Eko Istiyanto, M.Sc. (2) Prof. Drs. Agus Harjoko, M.Sc., Ph.D. (3) Dr. Agfianto Eko Putra, M.Si. (4) |
| Date | : | 0 2014 |
| Keyword | : | FPGA, Fault Tolerance, Dynamic Partial Reconfiguration. FPGA, Fault Tolerance, Dynamic Partial Reconfiguration. |
| Abstract | : | Field Programmable Gate Array (FPGA) is susceptible from hazardous radiation that leads to be in error state. In order to avoid that condition, we apply a fault tolerance technique. Most of the fault tolerances today are only using one mode, which means the fault tolerance that is applied will run all the time without changing its design. It does not consider the condition whether the hazard radiation will occur more frequently or not. As researches have shown, in the orbit, the hazard radiation happens in the South Atlantic Anomaly (SAA)frequently. Therefore, this project creates a new methodology in implementation of fault tolerance by using dual mode. When radiation is happened frequently, we apply more robust fault tolerance; if not frequent, we apply simple fault tolerance. A robust fault tolerance will use more resources, and simple fault tolerance will use less resources. Configuration in FPGA is done by Dynamic Partial Reconfiguration (DPR), which means the transition from robust to simple fault tolerance or vice versa is done while the system is running. This paper will talk about the technical implementation of dual mode fault tolerance by presenting systematically order and important aspect to implement the design successfully. The paper shows a result that dual mode fault tolerance can be configured in FPGA successfully. |
| Group of Knowledge | : | Sistem Informasi Geografi (SIG) |
| Original Language | : | English |
| Level | : | Internasional |
| Status | : |
Published
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